In order to make an ultrafine MISFET having a gate length of 30 nm or less, a transistor having a three-dimensional structure, for example, a nanowire type transistor (hereinafter also referred to as a nanowire transistor) is expected instead of a planar transistor of the background art. For example, for a nanowire transistor in which an SOI layer is used as a channel, a gate insulating film and a gate electrode are formed in a side surface and an upper surface of a silicon narrow portion (silicon nanowire) connected to a silicon wide portion. An extension region is formed in the narrow portion while a channel region below the gate electrode is interposed there between. A source-drain region is formed in the silicon wide portion.
A nanowire transistor has a strong gate controlling power and a high short-channel-effect immunity because the channel region is covered with the gate. Because all the three surfaces of the silicon nanowire, namely, the upper surface and both the side surfaces operate as the channel, the silicon nanowire is also called a tri-gate transistor.
In the nanowire transistor, a leakage current can be suppressed in an off-state because of the high short-channel-effect immunity. However, unfortunately a drain current may be reduced in an on-state because of a high parasitic resistance in the narrow portion. A silicon nanowire region where the gate electrode is not formed is effectively shortened in order to reduce the parasitic resistance. However, during lithographically forming a silicon nanowire pattern, when the wide portion is brought close to the gate electrode direction in order to shorten the silicon nanowire, it is difficult to make a width of the silicon nanowire small due to a proximity effect.
A Fin type channel transistor (hereinafter also referred to as a FinFET) is also widely studied as the transistor having the three-dimensional structure. In the FinFET, only the side surfaces of a Fin layer corresponding to the silicon nanowire of the nanowire transistor operate as the channel. The upper surface of the Fin layer is covered with a thick hard mask. Therefore, the upper surface does not operate as the channel. Unfortunately the parasitic resistance may be increased because the width of the Fin layer is narrow like the nanowire transistor.
A technology of selectively performing silicon epitaxial growth on the Fin layer in the region where the gate electrode is not formed has been disclosed. According to the technology, the parasitic resistance can be reduced because of an increased sectional area in the Fin layer.